Integrated circuit die are typically coupled to their packaging using one of several different techniques. In the case of wire bonding, the integrated circuit die is attached to a chip carrier or substrate using either an organic conductive adhesive or a solder. Then, small wires are attached (using electrical current or ultrasonic energy) between contact pads on the die and contact pads on the chip carrier using a wire bonding tool. The die is attached to the carrier face up, then a wire is bonded first to the die, then looped and bonded to the carrier. Wires can be several mm in length, and 25–35 μm in diameter.
An increasingly popular die-to-package bonding technique is to use flip chip technology. Flip chip is not a specific package or even a package type (like BGA), rather it describes the method of electrically connecting the die to the package carrier. The package carrier, either substrate or lead frame, then provides the connection from the die to the exterior of the package. The interconnection between the die and carrier in flip chip packaging is made through conductive bumps that are placed directly on the die surface. The bumped die is then flipped over and placed face down, with the bumps connecting to the carrier directly. A bump is typically 70–100 μm high, and 100–125 μm in diameter. The flip chip connection is generally formed one of two ways: using solder or using conductive adhesive. The solder bumped die is attached to a substrate by a solder reflow process, very similar to the process used to attach BGA balls to the package exterior. After the die is soldered, underfill is added between the die and the substrate. The chip attach and underfill steps are the basics of flip chip interconnect. Beyond this, the remainder of package construction surrounding the die can take many forms and can generally utilize existing manufacturing processes and package formats.
Certain substrate, device, and processing defects inevitably lead some of the integrated circuit die to be “bad” (i.e., not fully functional). Because of the high cost of cutting integrated circuit wafers into individual die, packaging the die, and testing the packaged integrated circuit, integrated circuit die are typically tested before being mounted on the supporting substrate. Die testing typically involves using a testing device or probe to make a plurality of discrete connections to the bond pads or bump contacts on the die and providing test signals (e.g., power and data signals) to the integrated circuit. Unfortunately, such physical contact between test probe and die can cause damage to the bond pads and/or bumps. This damage may ruin a die or in extreme cases an entire wafer.
One solution to this problem is to include both bond pads (i.e., pads to which bumps will be attached) and separate test pads for one or more of the bond pads. Each test pad is in electrical communication with a respective one of the bond pads. The substrate is tested using the test pads or some combination of test pads and bond pads. Thus, a testing device can contact the test pads without contacting the bond pads, avoiding the aforementioned damage. Examples of such solutions can be found in the U.S. patent application entitled “Semiconductor Component Having Test Pads and Method and Apparatus for Testing Same,” Ser. No. 10/842,770, naming M. H. Mardi et al., as inventors, and filed on May 11, 2004, (“the '770 application”) which is hereby incorporated by reference herein in its entirety.
Unfortunately, conventional die probing devices, e.g., existing vertical or cantilever probe cards, are not designed for use with dies including both bond and test pads. Accordingly, it is desirable to have die probing devices configured for use with integrated circuit dies having both bond pads and associated test pads.